摘要 :
In this paper the energy consumption of flash floating gate cell, during a channel hot electron operation, is investigated. We characterize the device using different ramp and box pulses on control gate, to find the best solution ...
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In this paper the energy consumption of flash floating gate cell, during a channel hot electron operation, is investigated. We characterize the device using different ramp and box pulses on control gate, to find the best solution to have low energy consumption and good cell performances. We use a new dynamic method to measure the drain current absorption in order to evaluate the impact of different bias conditions, and to study the cell behavior. The programming window and the energy consumption are considered as fundamental parameters. Using this dynamic technique, three zones of work are found; it is possible to optimize the drain voltage during the programming operation to minimize the energy consumption. Moreover, the cell's performances are improved using the CHISEL effect, with a reverse body bias. After the study concerning the programming pulses adjusting, we show the results obtained by increasing the channel doping dose parameter. Considering a channel hot electron programming operation, it is important to focus our attention on the bitline leakage consumption contribution. We measured it for the unselected bitline cells, and we show the effects of the lightly doped drain implantation energy on the leakage current. In this way the impact of gate induced drain leakage in band-to-band tunneling regime decreases, improving the cell's performances in a memory array.
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摘要 :
As the technology scales down to 90 nm and below, static random access memory (SRAM) standby leakage power is becoming one of the most critical concerns for low power applications. In this article, we review three major leakage cu...
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As the technology scales down to 90 nm and below, static random access memory (SRAM) standby leakage power is becoming one of the most critical concerns for low power applications. In this article, we review three major leakage current components of SRAM cells and also discuss some of the leakage current reduction techniques including body biasing, source biasing, dynamic V_(DD), negative wordline, and bitline floating schemes. All of them are achieved by controlling different terminal voltages of the SRAM cell in standby mode. On the other hand, performance loss occurs simultaneously with leakage saving. To validate the effectiveness of low power techniques, the leakage current, static noise margin, and read current of SRAM cells, based on the UMC 55 nm CMOS process with leakage current reduction techniques has been simulated. The results indicate that by using the dynamic V_(DD) and source biasing schemes, greater leakage suppressing capability, although with a higher performance loss, can be obtained. Therefore, the SRAM cell optimization scheme must consider the trade-off between power consumption and speed performance.
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In this paper, we embedded a Flash memory cell with 90-nm ground-rules in a high-performance CMOS logic process. A novel deep trench isolation (DTI) module enables an isolated p-well (IPW) bias scheme, leading to Flash with unifor...
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In this paper, we embedded a Flash memory cell with 90-nm ground-rules in a high-performance CMOS logic process. A novel deep trench isolation (DTI) module enables an isolated p-well (IPW) bias scheme, leading to Flash with uniform channel program/erase by Fowler–Nordheim tunneling without gate induced drain leakage, a key feature for low-power portable electronics. The IPW concept leads to a compact cell design and a highly scalable high-voltage periphery through the narrow intrawell and interwell isolation spaces. The memory arrays are defined by DTI of each bitline (BL) from its neighboring BLs. We additionally present a buried BL (BBL) concept that links the source contacts of each individual BL via the IPW; thus, effectively eliminating one metal line per BL and reducing overall cell size. A conservative cell size shrink of about 40% can be achieved for a uniform channel program/erase-Flash cell with deep trench and BBL compared to a conventional $ hbox{21F}^{2}$ cell.
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摘要 :
In this letter, new limitations on the NOR flash cell scaling have been presented. As cell scaling is continued, a parasitic capacitance between floating gate and bitline contact induces a large disturbance to the Fowler-Nordheim ...
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In this letter, new limitations on the NOR flash cell scaling have been presented. As cell scaling is continued, a parasitic capacitance between floating gate and bitline contact induces a large disturbance to the Fowler-Nordheim tunneling characteristics due to a coupling ratio variation, resulting in a much broader erase threshold distribution. Theoretical analysis including MEDICI simulations confirms the effects of parasitic capacitance on the erase threshold of NOR flash cells.
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摘要 :
A 3-dimensional double stacked 4 gigabit multilevel cell NAND flash memory device with shared bitline structure have successfully developed. The device is fabricated by 45 nm floating-gate CMOS and single-crystal Si layer stacking...
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A 3-dimensional double stacked 4 gigabit multilevel cell NAND flash memory device with shared bitline structure have successfully developed. The device is fabricated by 45 nm floating-gate CMOS and single-crystal Si layer stacking technologies. To support fully compatible device performance and characteristics with conventional planar device, shared bitline architecture including Si layer-dedicated decoder and Si layer-compensated control schemes are also developed. By using the architecture and the design techniques, a memory cell size of 0.0021 mum2/bit per unit feature area which is smallest cell size and 2.5 MB/s program throughput with 2 kB page size which is almost equivalent performance compared to conventional planar device are realized.
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摘要 :
We present a dynamic body charge modulation technique to improve
the matching of CMOS device threshold voltage (Vt)
characteristics in the partially depleted silicon-on-insulator (SOI)
technology. For a latch-type sense amplifier ...
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We present a dynamic body charge modulation technique to improve
the matching of CMOS device threshold voltage (Vt)
characteristics in the partially depleted silicon-on-insulator (SOI)
technology. For a latch-type sense amplifier in the SRAM complementary
bitline structure, a pair of-charging FETs are employed to bring the
bodies of cross-coupled sensing devices to the voltage rail. In doing
so, operating history-dependent body potential mismatches are eliminated
for every access cycle. Body-contacted FETs are returned to their
floating body states when the charging action is completed. This
technique achieves repeatable low-Vt and high-performance
operation simultaneously. The pulse signal controlling body charging is
not constrained by a stringent timing requirement. Therefore, its
effectiveness is insensitive to the body contact quality of sensing
FETs. This technique demonstrates a significant leverage for
high-performance RAM circuits. It also offers the advantages of speed
and noise immunity in the low-voltage low-power operating regime
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摘要 :
This paper introduces a high-performance voltage-scalable SRAM design in a 32 nm strain-enhanced high-k + metal-gate logic CMOS technology. The 291 Mb SRAM design features a 0.171 ¿m2 six-transistor bitcell that supports a broa...
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This paper introduces a high-performance voltage-scalable SRAM design in a 32 nm strain-enhanced high-k + metal-gate logic CMOS technology. The 291 Mb SRAM design features a 0.171 ¿m2 six-transistor bitcell that supports a broad range of operating voltages for low-power and high-frequency embedded applications. The tileable 128 kb SRAM subarray achieves 72% array efficiency with 4.2 Mb/mm2 bit density, and consumes 5 mW of leakage power at the supply voltage of 1 V. The design provides 4 GHz and 2 GHz of operating frequencies at the supply voltages of 1.0 V and 0.8 V, respectively. The integrated power management scheme features close-loop memory array leakage control, floating bitline, and wordline driver sleep transistor, resulting in a 58% reduction in subarray leakage power consumption.
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